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? semiconductor msm7502 1/35 ? semiconductor msm7502 multi-function pcm codec general description the msm7502, developed especially for low-power and multi-function applications in touch- tone telephone sets and digital telephone terminals of digital pbxs, is a single +5 v power supply codec device. the device consists of the analog speech paths directly connectable to a handset, the calling circuit directly connectable to a piezosounder, the push-button key scanning interface between push buttons and control processors, the dial tone generator, the m -law/a-law codec, and the processor interface. the functions can be controlled via 8-bit data bus. for the codec of the msm7502, an msm7543 is used as a core codec, so the msm7502 provides the available bit clock range wider than the family product msm6895. in addition, the msm7502 performs the greater key interface function and offers the upgraded side-tone level, receive level, and speaker pre-amplifier output level. features ? single +5 v power supply ? low power dissipation power on mode : 30 mw typ. 53 mw max. power saving mode : 2 mw typ. 5 mw max. ? in compliance with itu-ts companding law ? transmission clocks : 64, 128, 256, 512, 1024, 2048 khz 96, 192, 384, 768, 1536, 1544 khz ? built-in pll ? built-in reference voltage supply ? calling tone interval : controlled by processor ? calling tone combination : controlled by processor, 6 modes ? calling tone volume : controlled by processor, 4 modes ? ringing tone interval : controlled by processor ? ringing tone frequency : controlled by processor, 6 modes ? ringing tone level : controlled by processor, 4 levels ? built-in pb tone generator ? built-in speech path control switches ? general latch output for external control : 2 bits ? watch-dog timer : 500 ms ? key scanning i/o output : 8 bits input : 8 bits ? direct connection to handset : 1.2 k w driving available ? built-in pre-amplifier for loud-speaker ? hand-free interface ? m -law/a-law switchable codec ? lcd deflection angle voltage : controlled by processor, 8 levels ? package : 80-pin plastic qfp (qfp80-p-1420-0.80-bk) (product name : MSM7502GS-BK) e2u0023-28-81 this version: aug. 1998 previous version: nov. 1996
? semiconductor msm7502 2/35 block diagram ++C C C C C C + tpai cao tpao 20 db vol 9 vol 8 mpai mpao mpbo to tpbi mpbi mldyi sw 1 sw 2 sw 12 sw 7 sw 16 0 db ain aout vol 10 vol 1 pll pb gen. r-tone gen. f-tone gen. s-tone gen. wamble tone 1 khz latch vlcd gen. key intf scanning output scanning input 1000 hz 800 hz 400 hz 400 425 440 450 400*16 400*20 vol 2 C8.7 db 0 db vol 7 sw 5 sw 5 sw 10 vol 6 vol 5 C22 db vol 11 vol 12 vol 13 sw 21 sw 15 sw 11 sw 20 sw 19 sg gen. va vd ag dg sgt sgc po0 to po7 pi0 to pi7 0 db 0 db C3 db C6.8 db sw 6 sw 8 sw 18 sw 3 sw 4 sw 17 sw 14 sw 13 sw 9 0 db m /a codec 5.7 db vol 3 vol 4 cai r1i r2i rpo rmi rmo0 rmo1 spi spo sa0 sa1 pcmout pcmin bclock xsync rsync wrn rdn cen resetn d0 to d7 ad0 ad1 intt timen la lb lml vlcd C C processor intf
? semiconductor msm7502 3/35 pin configuration (top view) 64 41 lml la lb vlcd sa1 sa0 dg ag rmo1 rmo0 rmi spi spo rpo r2i r1i mldyi mpbo mpbi mpao mpai vd pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0 po0 po1 po3 po4 po5 po6 po7 pcmout bclock xsync pcmin po2 rsync tpbi tpao tpai sgt to va cai sgc cao timen resetn rdn wrn ad1 ad0 db6 db4 db1 intt cen db7 db5 db3 db2 db0 63 62 61 60 59 58 57 56 54 53 51 50 49 48 47 46 45 44 42 52 43 55 1 24 2 3 4 5 6 7 8 9 11 12 14 15 16 17 18 19 20 21 23 13 22 10 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 nc nc nc nc nc nc nc nc nc nc nc nc nc : no connect pin 80-pin plastic qfp
? semiconductor msm7502 4/35 pin and functional descriptions la, lb general latch outputs for external control. statuses of these outputs are controlled via the processor interface. refer to the description of the control data for details. these outputs provide the capability to drive one ttl. dg digital ground. dg is separated from the analog ground ag inside the device. but, dg should be connected as close to the ag pin on pcb as possible. ag analog ground. sa0, sa1 sounder (calling tone) driving outputs. the output signal on sa1 is inverted against the signal on sa0. the sounder circuit can be easily configured by connecting a piezo-sounder between sa0 and sa1. through processor control, the calling tone volume is selectable from four levels and one of six tone combinations is selectable. initially, the ringing tone volume is set at a maximum and the tone combination is set at a 16 hz wamble tone by a combination of 1 khz and 1.3 khz. if these pins are used with no-load, tone volume cannot be controlled. when tone volume control is required, a load resistor must be connected between sa0 and sa1.
? semiconductor msm7502 5/35 rmi, rmo0, rmo1 receive main amplifier input and outputs. rmi is the inverted input and rmo0 and rmo1 are the outputs of the receive main amplifier. the output signal on rmo1 is inverted against rmo0 by a gain 1 (0 db), so the earphone of a handset is directly connected between rmo0 and rmo1. during the system power down, the rmo0 and rmo1 outputs are in a high impedance state. the receive main amplifier gain is determined by a resistor connected between rpo and rmi, and a resistor connected between rmi and rmo0. the receive main amplifier gain varies between 0 and +20 db in effect. a piezo- receiver with an impedance greater than 1.2 k w is available. if the adjusting of receive path frequency characteristics is required, insert the following circuit for adjustment. during the whole system power on, the speech path from rmi to rmo0 and rmo1 is disconnected and the output of rmo0 and rmo1 is at the sg level (va/2). the speech path is provided by processor control. a circuit example for adjustment of frequency characteristics rpo rmi r1 rmo0 main amplifier gain without capacitors g= r2 r1 c1 r2 c2
? semiconductor msm7502 6/35 spi addit0ion input of speaker amplifier. the typical gain between spi and spo is 0 db. but, the 2-stage gain amplifier allows to set up a gain between 0 db and C18 db in a 6 db step, or a gain between 0 db and C28 db in a 4 db step through processor control. the input resistance of spi is typically 20 k w to 150 k w (it varies by gain setting). spo output of pre-amplifier for speaker. since the driving capability is 2.4 v pp for the load of 20 k w , spo can not directly drive a speaker. during the whole system power down mode, spo is at an analog ground level. during the whole system power on mode, spo is in a non-signal state (sg level), and a receive voice signal, r-tone, f-tone, hold acknowledge tone, pb signal acknowledge tone, and sounder tone are output from the speaker by processor control. when the speaker is used as a sounder, the sounder tone is output via the spo pin by connecting the spi input with the sounder output (sa0 or sa1). in addition, when the ad-converted sounder tone is sent from the main device, the sounder tone is output via the spo pin since the cao pin for codec output is internally connected. r1i, r2i, rpo r1i and r2i are for the inputs and rpo is for the output of the receive pre-amplifier. normally, r1i is connected via an ac-coupling capacitor to the codec analog output (cao), and r2i is used as the mixing signal input pin. the typical gain between r1i and pro is C6 db. through processor control, gains are variable from C14 db to 0 db in 2 db steps. in addition, the receive pad can control the gain of C9, C6, C3, or 0 db. the gain between r2i and rpo is fixed to 0 db. during the whole system power-on mode, the rpo output is in non-signal state, and speech signal, r-tone, f-tone, pb acknowledge tone, side tone signal are output by processor control. during the whole system power-down mode, the rpo output is the analog ground level. the input resistance of r1i is typically between 20 k w and 100 k w (it varies by gain setting). the input resistance of r2i is typically 20 k w . mldyi hold tone signal input. for example, the output of external melody ic is connected to this pin. through processor control, the signal applied to mldyi is output from the to output pin as a hold tone on the transmit path, and from the spo output pin as a hold acknowledge tone on the receive path. the typical gain between mldyi and to is C2 db. through processor control, a gain between C2 db and C11 db is also settable at 3 db steps. the typical gain between mldyi and spo is C3 db. through processor control, a gain between C3 db to C31 db is also settable at 4 db steps. mldyi is a high impedance input, so insert an about 100 k w bias resistor between mldyi and sgt.
? semiconductor msm7502 7/35 tpbi, to tpbi is the input and to is the output of the transmit pre-amplifier (b). when the handset is used, tpbi is connected to the transmit pre-amplifier (a) output pin (tpao). if adjustment of frequency characteristics on the transmit path is required, insert a circuit for adjustment of characteristic between tpao and tpbi. through processor control, the signal applied to this pin is output via the to pin on the transmit path and its side tone via the rpo pin. during the whole system power down mode, to is at an analog ground level. the typical gain between tpbi and to is +17.7 db. through processor control, a gain between +17.7 db and +8.7 db is also settable at 3 db steps. the typical gain between tpbi and rpo is +3.0 db. through processor control, a gain between C9 db and +9 db is variable in 3 db steps. changing the gain between tpbi and to may change the gain between tpbi and rpo. tpbi is a high impedance input, so insert an about 100 k w resistor between tpbi and sgt. tpao tpbi sgt c3 r3 c4 r4 a circuit example for adjustment of frequency characteristics mpai, mpao handfree microphone pre-amplifier (a) input and output. mpai is the input and mpao is the output. the speech path between mpai and mpao is always active regardless of processor control. during the whole system power saving mode, mpao is at an analog ground level. the gain between mpai and mpao is typically +20 db. through processor control, gains between +14 db and +11 db are also settable. mpai is a high impedance input, so insert an about 100 k w between mpai and sgt. mpbi, mpbo the handfree microphone (b) input and output. mpbi is the inverted input and mpbo is the output. with an external resistance, the amplifier gain is adjusted in the range between C25 db and +25 db. a signal on the mpbo is output via the to pin through processor control. during the whole system power down mode, mpbo is at an analog ground level. the gain between mpbo and to is fixed to 0 db.
? semiconductor msm7502 8/35 tpai, tpao the transmit pre-amplifier input and output. tpai is the input and tpao is the output. tpai should be connected to the microphone of handset via an ac-coupling capacitor if the dc offset appears at a transmit signal (offset from sgt). the transmit path from tpai to tpao is always active regardless of processor control. during the whole system power down mode, tpao is at an analog ground level. the gain between tpai and tpao is fixed to 20 db. sgt transmit path signal ground. sgt outputs half the supply voltage. during the whole power down mode, sgt is in a high impedance state. sgc bypass capacitor connecting pin for signal ground level. insert a 0.1 m f high performance capacitor between sgc and ag. va, vd +5 v power supply. va is for an analog circuit and vd is for digital supply. connect both va and vd to the +5 v analog path of the system. cai, cao codec analog input and output. cai is the analog input of codec to be connected to the to pin. if the dc offset voltage on the to signal is great, cai should be connected via ac-coupling capacitor. at this time, insert an about 100 k w bias resistor between cai and sgt. cao is the analog output of codec. cao should be connected to r1i via ac-coupling capacitor. a bias resistor is not required to r1i. during the whole system or codec power down mode, cao is at the sg voltage level.
? semiconductor msm7502 9/35 bclock codec pcm data i/o shift clock input. the frequency is one of 64 khz, 128 khz, 256 khz, 512 khz, 1024 khz, 2048 khz, 96 khz, 192 khz, 384 khz, 786 khz, 1536 khz, and 1544 khz. if the bclock signal is not applied, pll is out of synchronization and the codec path goes into the power down mode. xsync, rsync synchronous signal input. codec pcm data is sent out sequencially via the pcmout pin from msb at the rising edge of the bclock signal in synchronization with the rise of the xsync signal. pcm data should be entered via the pcmin pin with msb at the head in synchronization with the rise of the rsync signal. pcm data is shifted in at the falling edge of the bclock signal. since the xsync signal is used for a trigger signal for pll and for a clock signal to the tone generator, if this signal is not applied, not only any tone can not be output, but also pll goes out of synchronization and the codec path goes into a power down mode. this signal has to be synchronous with the bclock signal and its frequency must be within 8 khz 50 ppm to ensure the codec ac characteristics (mainly frequency characteristics). pcmin pcm signal input. pcmin data is shifted in at the falling edge of the bclock signal and is latched into the internal register after eight bits are shifted. pcmout pcm signal output. pcmout data is shifted out at the rising edge of the bclock signal. pcmout is left open after eight bits are shifted or when pll goes out of synchronization. pcmout also is left open through processor control. in addition, a digital path between pcmin and pcmout is formed through processor control. pcmout needs a pull-up resistor because of its open-drain circuit.
? semiconductor msm7502 10/35 po0, po1, po2, po3, po4, po5, po6, po7 key scanning outputs. these output pins need external pull-up resistors because of their open- drain circuits. but, when these are used in combination with pi0 to pi7, pull-up resistors are not required. through processor control, these outputs can be set open or to digital "0". initially, these outputs are set at an opened state. pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7 key scanning inputs. in the read mode, data on pi0 to pi7 can be read out of the processor via data bus (db0 to db7). since these inputs are pulled up inside the ic, external resistors are not required. intt interrupt signal output to the processor. intt outputs interrupt signals (digital "0") at intervals of 8 ms by the interrupt release control signal from the processor. this output keeps digital "0" unless the interrupt is released. intt does not output any signal while no xsync signal is input. when the resetn signal is in "0" state, intt is in "1" state. intt goes from "1" state to "0" state 8 ms after the resetn signal goes to "1" state. interrupt release signal from processor intt output t < 8 ms 8 ms < t < 16 ms t < 8 ms 8 ms 16 ms 8 ms db0, db1, db2, db3, db4, db5, db6, db7 data bus inputs and outputs. these pins are configured as an output during the read mode only and as an input during other modes.
? semiconductor msm7502 11/35 ad0, ad1 address data inputs for the internal control registers. addressing of the internal control registers is executed by ad0 and ad1 and sub address data, db7 and db6. ad1 ad0 db7 db6 function 00 0 0 on/off controls of sounder, r-tone, f-tone 0 1 level/frequency controls of sounder, r-tone 1 0 pb tone control 11 controls of internal speech path switch and general latch watchdog timer reset 0 0 controls of receive gain and side tone gain 0 1 controls of transmit hold tone, pb tone, handfree input, handset inputs gain 1 0 controls of speaker pre-amplifier gain and additional speaker gain 1 1 controls of receive pad and incoming tone input gain 01 1 0 key scanning output control 1 1 0 0 key scanning interrupt reset 1 1 0 1 lcd deflection angle control voltage setting 1 1 1 0 power on/off control 1 1 1 1 codec control (controls of companding law and digital loop) 1 0 key scanning data read-out write read wrn write signal for internal control registers. data on the data bus is written into the registers at the rising edge of wrn under the condition of digital "0" of cen (chip enable). while cen is in digital "1" state, wrn becomes invalid. the write cycle is a minimum of 2 m s regardless of the presence or absence of clock signals. rdn read signal input to read pi0 to pi7 out of the processor. when cen and rdn are in digital "0" state, the digital values on pi0 to pi7 are output onto the data buses db0 to db7. while cen is in digital "1" state, the rdn signal becomes invalid.
? semiconductor msm7502 12/35 cen chip enable signal input. when cen is in digital "0" state, wrn and rdn are valid. resetn reset signal input. digital "0" input to resetn makes all of internal control registers to be initialized. when powered on, this resetn signal should be input for initializing the system. timen watchdog timer output. when the processor does not reset the timer, the 500 ms period (digital "0" : 4 ms) digital signal is continuously output. when resetn is at digital "0", this timer is reset. and, in about 500 ms after resetn goes to digital "1", the first timer output signal is issued and then the timer signal is output at intervals of a 500 ms. if the sync signal is not input, the timen signal is not output. lml control signal output for external hold tone generator. lml goes to digital "1" state when the hold tone transmit mode on transmit path or the hold acknowledge tone mode on receive path is selected. during initialized state, lml is in digital "0" state. vlcd by processor control, vlcd outputs a dc voltage between 0 and 1.7 v is about 0.25 v step. this is used to control the deflection angle of the lcd display. vlcd has the internal resistance value of about 1 k w , so the external load of over 100 k w should be used. during initialized state, vlcd outputs the voltage of 0 v.
? semiconductor msm7502 13/35 absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd 0 to 7 v analog input voltage v ain -0.3 to v dd + 0.3 digital input voltage v din -0.3 to v dd + 0.3 storage temperature t stg -55 to +150 ag, dg = 0 v ag, dg = 0 v ag, dg = 0 v v c v recommended operating conditions recommend operating conditions (analog interface) r al tpao, mpao, mpbo, to, 20 analog load resistance k w rmo0, rmo1 with respected to 0.6 c al tpao, mpao, mpbo, to, rpo, spo, cao 100 analog load capacitance rmo0, rmo1 70 pf nf tpai, tpbi, mpai C10 +10 mldy C50 +50 r1i, r2i, spi C25 +25 cai C100 +100 allowable analog input offset voltage v off mv min. max. parameter symbol condition typ. unit sg level rpo, spo, cao input high voltage v d va, vd (voltage must be fixed) 5.0 4.75 5.25 ta +25 C10 +70 power supply voltage v v ih all digital input pins 2.2 v dd v input low voltage v il all digital input pins 0 0.8 v operating temperature c digital input rise time t ir all digital input pins 50ns digital input fall time t if all digital input pins 50ns po0 to po7 pcmout 10 0.5 digital output load r dl k w po0 to po7 pcmout 100 c dl pf min. max. parameter symbol condition typ. unit
? semiconductor msm7502 14/35 recommended operating conditions (codec digital interface) recommended operating conditions (processor digital interface) p w write pulse period ns wrn 2000 t w write pulse width ns wrn 100 t r read pulse width ns rdn 200 ad0, ad1 ? wrn ns 10 t aw1 ad0, ad1 ? rdn ns 80 t ar1 address data setup time wrn ? ad0, ad1 ns 50 t aw2 rdn ? ad0, ad1 ns 10 t ar2 address data hold time cen ? wrn ns 10 t cw1 cen ? rdn ns 80 t cr1 cen setup time wrn ? cen ns 50 t cw2 rdn ? cen ns 10 t cr2 cen hold time db0 to 7 ? wrn data setup time ns 110 t dw1 wrn ? db0 to 7 data hold time ns 20 t dw2 resetn reset pulse width ns 110 t wres see fig.2 min. max. parameter symbol condition typ. unit f c 8.0 6.0 10.0 clock frequency khz 64, 128, 256, 512, 1024, 2048 96, 192, 384, 768, 1536, 1544 sync pulse frequency clock duty ratio f s d c bclock xsync, rsync bclock khz 50 40 60 % bclock ? x, rsync see fig.1 sync pulse setting time t xs 100 ns x, rsync ? bclock see fig.1 t sx 100 ns sync pulse width t ws xsync, rsync 1 bck 100 m s data setup time t ds pcmin 100 ns data hold time t dh pcmin 100 ns allowable jitter width xsync, rsync 500 ns min. max. parameter symbol condition typ. unit
? semiconductor msm7502 15/35 electrical characteristics dc and digital interface characteristics i dd1 operating mode (no signal, sounder off) 6.0 10.0 power supply current ma (v dd = 5 v 5%, ta = C10c to +70c) i dd2 whole system power down 0.4 0.8 ma i dd3 codec power down 2.8 5.0 ma input high voltage v ih 2.2 v dd v input low voltage v il 0.0 0.8 v digital pins except for pi0 to pi7 2.0 m a i ih pi0 to pi7 (internal pull-up pins) 2.0 m a high input leakage current digital pins except for pi0 to pi7 0.5 m a i il pi0 to pi7 (internal pull-up pins) 10 25 m a low input leakage current i oh = 0.4 ma i oh = 1 m a 2.4 3.8 digital output high voltage v oh v i ol = C1.6 ma 0.0 digital output low voltage v ol 0.4 v pcmout, db0 to db7 (write mode) digital output leakage current i o 10 m a tpao, mpao, mpbo, to, cao, rpo, rmo0, rmo1, spo analog output offset voltage v off C100 +100 mv input capacitance c in 5 pf tpai, tpbi, mldyi, rmi, mpai, mpbi 10 m w r1i, r2i, spi 10 k w cai (fin : < 4 khz) 1 m w analog input resistance r in va/2 C0.05 va/2 +0.05 sg voltage va/2 v i sgf force current 1.5 1.0 i sgs sink current 0.5 0.3 sg drive current ma equivalent pull-up resistance r pull pi0 to pi7, v i = 0 v 370 200 500 k w v dd v dd min. max. parameter symbol condition typ. unit
? semiconductor msm7502 16/35 ac characteristics 1 (codec) loss t1 loss t2 loss t3 loss t4 loss t5 loss t6 transmit frequency response db parameter symbol condition typ. unit min. max. freq. (hz) level (dbm0) 60 300 1020 2020 3000 3400 27 +0.07 C0.03 +0.06 0.38 20 C0.20 C0.15 C0.15 0.0 +0.20 +0.20 +0.20 0.80 0 reference loss r1 loss r2 loss r3 loss r4 loss r5 300 1020 2020 3000 3400 C0.03 C0.02 +0.15 0.56 C0.15 C0.15 C0.15 0.0 +0.20 +0.20 +0.20 0.80 reference receive frequency response db 0 sd t1 sd t2 sd t3 sd t4 sd t5 43.0 41.0 38.0 31.0 26.5 35 35 35 29 24 db 1020 3 0 C30 C40 C45 transmit signal to distortion ratio *1 sd r1 sd r2 sd r3 sd r4 sd r5 43.0 41.0 40.0 34.0 31.0 37 37 37 30 25 db 1020 3 0 C30 C40 C45 receive signal to distortion ratio *1 gt t1 gt t2 gt t3 gt t4 gt t5 +0.01 C0.05 +0.05 +0.30 C0.2 C0.2 C0.4 C1.2 +0.2 +0.2 +0.4 +1.2 reference transmit gain tracking db 1020 3 C10 C40 C50 C55 gt r1 gt r2 gt r3 gt r4 gt r5 0.0 C0.10 C0.30 C0.40 C0.2 C0.2 C0.5 C1.2 +0.2 +0.2 +0.5 +1.2 reference receive gain tracking db 1020 3 C10 C40 C50 C55 (v dd = 5 v 5%, ta = C10c to +70c) note: *1 psophometric filter is used
? semiconductor msm7502 17/35 ac characteristics 1 (codec) (continued) tgd t1 tgd t2 tgd t3 tgd t4 tgd t5 transmit group delay ms 500 600 1000 2600 2800 0.19 0.12 0.02 0.05 0.08 0.75 0.35 0.125 0.125 0.75 0*4 tgd r1 tgd r2 tgd r3 tgd r4 tgd r5 receive group delay ms 500 600 1000 2600 2800 0.0 0.0 0.0 0.09 0.12 0.75 0.35 0.125 0.125 0.75 0*4 cr t transmit ? receive 78 70 cr r receive ? transmit 86 75 1020 0 crosstalk attenuation db 4.6 khz to 72 khz discrimination dis 0 to 4000 hz C25 32.0 30 db 300 to 3400 out-of-band signal spurious s 4.6 khz to 100 khz 0 C37.5 C35 dbmo fa = 470 fb = 320 intermodulation distortion imd 2faCfb C4 C52 C35 dbmo psr t *5 30 psr r 0 to 50 khz 50 mv pp power supply noise rejection ratio db parameter symbol condition typ. unit min. max. freq. (hz) level (dbm0) (v dd = 5 v 5%, ta = C10c to +70c) ain = sg *1 nidle t *2 C73.5 C71 C70 C69 *1 *3 nidle r C78.0 C75 idle channel noise dbmop av t 0.5671 0.6007 0.6363 av r 0.5671 0.6007 0.6363 1020 0 vrms absolute amplitude a to a bclock = 64 khz absolute delay time td 1020 0 0.58 0.60 ms notes: *2 upper is specified for the m-law, lower of the a-law *3 pcmin input : idle code *4 minimum value of the group delay distortion *5 the measurement under idle channel noise
? semiconductor msm7502 18/35 ac characteristics 2 (transmit path) gtpa pre-amp gain db 1020 C24.0 20.0 18.0 22.0 tpai-tpao tpbi-to set at typical gain gtpb1 transmit path gain db 17.7 15.7 19.7 C3 db C6 db C9 db for typical setting rg1tpb rg2tpb rg3tpb C3.0 C6.0 C9.0 C5.0 C8.0 C11.0 C1.0 C4.0 C7.0 transmit path gain setting (vol8) db mpai-mpao set at typical gain gmpa db 20.0 18.0 22.0 microphone pre-amp gain for typical setting C6 db C9 db rg1mpa rg2mpa C6.0 C9.0 C8.0 C11.0 C4.0 C7.0 db microphone pre-amp gain setting (vol9) 1020 C24.0 additional transmit signal gain gtmx 1020 C4.0 mpbo-to 0.0 C2.0 +2.0 db to per wave set at typical gain in-channel pb signal output level vpbt1 C17.4 C19.4 C15.4 dbv C3 db C6 db C9 db for typical setting gpbt1 gpbt2 gpbt3 C3.0 C6.0 C9.0 C5.0 C8.0 C11.0 C1.0 C4.0 C7.0 db in-channel pb signal output level setting (vol4) in-channel pb signal frequency deviation dfpbt C1.0 +1.0 % mldyi-to set at typical gain hold tone path gain gpat 1020 C4.0 C2.0 C4.0 0.0 db C3 db C6 db C9 db for typical setting rg1pat rg2pat rg3pat C3.0 C6.0 C9.0 C5.0 C8.0 C11.0 C1.0 C4.0 C7.0 db hold tone path gain setting (vol3) tpai:terminated in 510 w measured at to tpao-tpbi directly connected set at typical gain *6 idle channel noise nitpa C75 dbv tpao, to, mpao, mpbo r l = 20 k w maximum output voltage swing vot 1020 2.4 v pp in-channel pb signal distortion thdpbt in-band distortion C35 C30 db parameter symbol condition typ. unit min. max. freq. (hz) level (dbv) (v dd = 5 v 5%, ta = C10c to +70c) note: *6 noise band width: 0.3 khz to 3.4 khz, non-weighted
? semiconductor msm7502 19/35 ac characteristics 3 (receive main amp.) dgrmo receive main amp output gain difference db 1020 C4.4 C0.10 rmo0/rmo1 gain = 1 dprmo receive main amp output phase difference deg 1020 C4.4 C179.6 rmo0/rmo1 1.2 k w between rmo0 and rmo1. measured at each output vrmo v pp 1020 3.6 maximum amplitude parameter symbol condition typ. unit min. max. freq. (hz) level (dbv) (v dd = 5 v 5%, ta = C10c to +70c) ac characteristics 3 (receive path) receive signal path gain db 1020 C4.0 C6.0 C8.0 C4.0 typical gain is set between r1i and rpo receive signal path gain setting (vol1) db receive pad gain setting (vol10) db additional receive signal path gain grmx db 0.0 C2.0 +2.0 r2i and rpo C4.0 1020 gside side tone path gain db 1020 C14.0 3.0 1.0 5.0 typical gain is set betweentpbi and rpo side tone path gain setting (vol2) db typical gain is set between rpo and spo speaker pre-amp gain gsp db 0.0 C2.0 +2.0 1020 C4.0 speaker pre-amp gain setting (vol5) db additional speaker input path gain typical gain is set between spi and spo gspi db 0.0 C2.0 +2.0 C4.0 1020 grpa C8 db C6 db C4 db C2 db 2 db 4 db 6 db for typical setting rgrpa1 rgrpa2 rgrpa3 rgrpa4 rgrpa5 rgrpa6 rgrpa7 C8.0 C6.0 C4.0 C2.0 2.0 4.0 6.0 C10.0 C8.0 C6.0 C4.0 0.0 2.0 4.0 C6.0 C4.0 C2.0 0.0 4.0 6.0 8.0 for typical setting C3 db C6 db C9 db C3.0 C6.0 C9.0 C5.0 C8.0 C11.0 C1.0 C4.0 C7.0 rgpad1 rgpad2 rgpad3 6 db 3 db C3 db C6 db C9 db C12 db for typical setting rgside1 rgside2 rgside3 rgside4 rgside5 rgside6 6.0 3.0 C3.0 C6.0 C9.0 C12.0 4.0 1.0 C5.0 C8.0 C11.0 C14.0 8.0 5.0 C1.0 C4.0 C7.0 C10.0 C4 db C8 db C12 db C16 db C20 db C24 db C28 db for typical setting rgsp1 rgsp2 rgsp3 rgsp4 rgsp5 rgsp6 rgsp7 C4.0 C8.0 C12.0 C16.0 C20.0 C24.0 C28.0 C6.0 C10.0 C14.0 C18.0 C22.0 C26.0 C30.0 C2.0 C6.0 C10.0 C14.0 C18.0 C22.0 C26.0 parameter symbol condition typ. unit min. max. freq. (hz) level (dbv) (v dd = 5 v 5%, ta = C10c to +70c)
? semiconductor msm7502 20/35 ac characteristics 3 (receive path) (continued) gpar hold acknowledge tone path gain db C3.0 C5.0 C1.0 typical gain is set between mldyi and spo pb acknowledge tone output level dbv C10 db C20 db setting, than typical gain vpbrp C30.1 C32.1 C28.1 1020 C4.0 rpo per wave spo per wave set at typical gain dbv vpbsp C28.2 C30.2 C26.2 dfpbr pb acknowledge tone frequency difference % C1.0 +1.0 rpo, spo thdpbr pb acknowledge tone distortion db C35 C30 rpo, spo typical gain is set between cao and spo incoming tone speaker output path gain gcao db 0.0 C2.0 +2.0 1020 C20 incoming tone speaker output path gain setting (vol11) rgcao1 rgcao2 C10.0 C20.0 C12.0 C22.0 C8.0 C18.0 db r1i:sg, measured at rpo set at typical gain. *6 nirpo dbv C86.0 r1i:sg, measured at spo set at typical gain. *6 nispo dbv C89.0 r1i:sg, gain 0 db rmo0, rmob *6 nirmo dbv C86.0 idle channel noise rpo, spo r l = 20 k w vor maximum output amplitude v pp 2.4 parameter symbol condition typ. unit min. max. freq. (hz) level (dbv) (v dd = 5 v 5%, ta = C10c to +70c) additional speaker input path gain setting (vol6) C4.0 1020 rgspi1 rgspi2 rgspi3 setting, than typical gain C6 db C12 db C18 db C6.0 C12.0 C18.0 C8.0 C14.0 C20.0 C4.0 C10.0 C16.0 db note: *6. noise band width : 0.3 khz to 3.4 khz, non weighted ac characteristics 4 (ringing tone) vrto r-tone output amplitude (vol7) mv pp 90 120 150 180 63 84 105 126 117 156 195 234 level setting 1 level setting 2 level setting 3 level setting 4 rpo vftrp rpo 160 112 208 vftsp spo 11.0 7.5 14.5 f-tone output amplitude mv pp 0 db C10 db C20 db gain setting 220 70 17 154 49 12 286 91 22 vstsp spo s-tone output amplitude (vol12) mv pp (v dd = 5 v 5%, ta = C10c to +70c) min. max. parameter symbol condition typ. unit
? semiconductor msm7502 21/35 ac characteristics 4 (sounder output circuit) vst1 vst2 vst3 vst4 sounder tone output amplitude (vol13) v pp 4.0 1.28 0.47 0.28 3.25 0.73 0.25 0.13 1.98 0.65 0.45 vol.1 vol.2 vol.3 vol.4 730 w between sa0 and sa1. measured at each out parameter symbol condition typ. unit min. max. freq. (hz) level (dbv) (v dd = 5 v 5%, ta = C10c to +70c) lcd defelection angle control voltage output vlcd output voltage v 1.70 1.50 1.30 1.10 0.85 0.55 0.30 0.0 1.40 1.25 1.05 0.85 0.65 0.35 0.15 0.0 2.00 1.75 1.55 1.35 1.05 0.75 0.45 0.05 db2 1 1 1 1 0 0 0 0 db1 1 1 0 0 1 1 0 0 db0 1 0 1 0 1 0 1 0 output resistance rolcd 1.0 k w output load rllcd 100 k w to gnd (v dd = 5 v 5%, ta = C10c to +70c) min. max. parameter symbol condition typ. unit digital interface characteristics t pdla digital output (latch) delay time m s 0.2 1.5 wr ? la, lb wr ? po0 to po7 pull-up resistance : 10 k w key scanning output delay time t pdscn m s 0.2 1.5 t pddata digital output (data) delay time ns 52 20 150 rd ? db0 to db7 bclock ? pcmout pull-up resistance : 500 w codec data output delay time t pdcod ns 50 20 100 (v dd = 5 v 5%, ta = C10c to +70c) min. max. parameter symbol condition typ. unit
? semiconductor msm7502 22/35 timing diagram codec timing bclock xsync pcmout bclock rsync pcmin 1 23456 78 t pdcod msb b2 b3 b4 b5 b6 9 b7 b8 t sx t xs t ws t ds t dh 1 23456 789 t sx t xs t ws codec transmit timing codec receive timing msb b2 b3 b4 b5 b6 b7 b8 figure 1 processor interface timing ad0, ad1 cen wrn rdn db0 to db7 po0 to po7 latch output t cw1 t cw2 t w t pddata t pddata t pdscn t pdla t aw1 t aw2 t ar1 t ar2 t cr1 t cr2 t r t dw1 t dw2 figure 2
? semiconductor msm7502 23/35 functional description control data description sounder and tone on/off control write mode address data ad1 = 0, ad0 = 0 db7 sounder output on sw19 on sw15 off, db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 1 0 1 0 1 0 1 0 1 0 00 00 01 01 10 10 11 11 11 11 00 0 00 0 1 sounder output off sw19 off sounder output on sw20 on sounder output off sw20 off r-tone on sw13 on r-tone off sw13 off f-tone on(1 khz) sw14 on, sw15 off, f-tone off sw14 off, sw15 on, f-tone on(1 khz) sw14 off, sw15 off, f-tone off sw14 off, tone output: sa0, sa1 tone output: spo *1 tone output: rpo tone output: spo *1: this sounder output is sent at the timing shown below. on off on off 0.25 s 0.125 s 0.625 s 2 s
? semiconductor msm7502 24/35 level and frequency control of sounder and r-tone write mode address data ad1 = 0, ad0 = 0 db7 sa0, sa1 outputs sounder volume 1 (large) db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 0 00 01 10 11 01 00 0 sa0, sa1 outputs sounder volume 2 (middle) sa0, sa1 outputs sounder volume 3 (small 1) sa0, sa1 outputs sounder volume 4 (small 2) sounder combination tone 1 (16 hz wamble tone with 1000 hz/1333 hz) sounder combination tone 2 (16 hz wamble tone with 667 hz/800 hz) sounder combination tone 3 (8 hz wamble tone with 800 hz/1000 hz) sounder combination tone 4 (single tone of 1000 hz) sounder combination tone 5 (single tone of 800 hz) sounder combination tone 6 (single tone of 400 hz) sounder volume and tone are defind at a time. 01 0 10 0 00 1 01 1 10 1 r-tone output level 1 (90 mv pp at rpo output) 1 00 01 10 11 00 0 r-tone output level 2 (120 mv pp at rpo output) r-tone output level 3 (150 mv pp at rpo output) r-tone output level 4 (180 mv pp at rpo output) r-tone 400 hz single tone r-tone 425 hz single tone r-tone 440 hz single tone r-tone 450 hz single tone r-tone 400 hz on/off by 16 hz r-tone 400 hz on/off by 20 hz 01 0 10 0 11 0 00 1 01 1 at the initial setting, sounder volume 1 and sounder combination tone 1 are set. sa0, sa1 sounder volume: vol 13 r-tone output level = vol 7 r-tone output level and frequency are defined at a time. at the initial setting, output level 1 and a single 400 hz tone are set.
? semiconductor msm7502 25/35 pb tone control write mode address data ad1 = 0, ad0 = 0 db7 db6 db5 db4 db3 db2 db1 db0 control data remarks 00 01 10 11 10 01 when pbtc = 0 sw16: on sw17: on sw18: off 01 01 01 10 10 10 11 00 01 11 11 xx 00 00 00 00 10 10 11 11 00 01 10 11 00 01 10 11 xx pb 1 2 3 a 9 c * 0 4 5 6 b 7 8 # d pb tone stop high low 1209 hz 697 hz 1336 hz 697 hz 1477 hz 697 hz 1633 hz 697 hz 1209 hz 770 hz 1336 hz 770 hz 1477 hz 770 hz 1633 hz 770 hz 1209 hz 852 hz 1336 hz 852 hz 1477 hz 852 hz 1633 hz 852 hz 1209 hz 941 hz 1336 hz 941 hz 1477 hz 941 hz 1633 hz 941 hz output pb frequency sw16, sw17, sw18: off 00 1 pbtc pb tone is sent to the transmit path t0 and the receive path rpo. when pbtc = 1 sw16: off sw17: off sw18: on pb tone is sent to the receive path spo only.
? semiconductor msm7502 26/35 sw control and timer reset write mode address data ad1 = 0, ad0 = 0 db7 sw1 db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 1 01 10 11 01 11 0 when hold tone or pb tone transmit is selected, these inputs are muted. 01 01 10 10 10 11 00 01 10 11 above codes 00 00 01 00 00 00 10 11 11 11 10 11 00 01 10 11 00 00 on transmit handfree input sw2 on transmit handset input sw3 on receive input sw4 on side tone input sw5 on receive main amplifier input sw6 on receive speaker input sw7 on transmit path hold tone input sw8 on receive path hold tone acknowledge input sw9 on additional receive input sw10 on additional speaker input sw11 on speaker dec input sw12 on pcm output enable la = 1 lb = 1 general latch output for external control above corresponding sw or latch is set to off or "0". 00 0 0 all of above sws or latches are set to off or "0" at the initial setting stage. 1 1 watchdog timer is reset. 11 when handfree input is selected, side tone is muted. when either of sw7 or sw8 is set to on, external terminal lml goes to "1". speaker dec input = codec aout
? semiconductor msm7502 27/35 gain setting (receive gain, side tone gain) write mode address data ad1 = 0, ad0 = 1 db7 typical receive gain (C6db) db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 00 01 10 11 00 1 C8 db than the typical gain typical side tone gain (C9 db) receive gain = vol1 1 1 1 0 1 1 1 0 0 0 0 00 01 10 11 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 C6 db than the typical gain C4 db than the typical gain C2 db than the typical gain +2 db than the typical gain +4 db than the typical gain +6 db than the typical gain C12 db than the typical gain C9 db than the typical gain C6 db than the typical gain C3 db than the typical gain +3 db than the typical gain +6 db than the typical gain side tone off (vol2 max loss) side tone gain = vol2 receive gain and side tone gain are set at a time. at the initial setting, the typical gain is set.
? semiconductor msm7502 28/35 gain control (transmit hold tone, pb tone, microphone input, handset input) write mode address data ad1 = 0, ad0 = 1 db7 typical transmit hold tone gain (C2 db) db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 0 00 01 10 11 01 00 0 C3 db with respect to the typical gain transmit hold tone gain = vol3 01 10 11 1 10 11 10 11 01 00 01 00 C6 db with respect to the typical gain C9 db with respect to the typical gain typical transmit pb tone gain (+4 db) C3 db with respect to the typical gain C6 db with respect to the typical gain C9 db with respect to the typical gain typical handfree input gain (+20 db) C6 db with respect to the typical gain C9 db with respect to the typical gain typical handset input gain (+12 db) C3 db with respect to the typical gain C6 db with respect to the typical gain C9 db with respect to the typical gain transmit pb tone gain = vol4 hold tone gain and pb tone gain are set at a time. at the initial setting, the typical gain is set. handfree input gain = vol9 handset input gain = vol8 handfree input gain and handset input gain are set at a time. at the initial setting, the typical gain is set.
? semiconductor msm7502 29/35 gain control (receive pad, speaker) write mode address data ad1 = 0, ad0 = 1 db7 typical speaker amp. gain (0 db) db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 1 00 01 10 11 10 1 -4 db with respect to the typical gain speaker amp. gain = vol5 1 1 1 0 0 1 0 0 0 0 1 0 00 01 0 0 0 0 00 01 10 11 0 1 1 1 00 01 10 11 10 0 0 0 0 1 1 -8 db with respect to the typical gain -12 db with respect to the typical gain -16 db with respect to the typical gain -20 db with respect to the typical gain -24 db with respect to the typical gain -28 db with respect to the typical gain typical additional speaker input path gain (0 db) -6 db with respect to the typical gain -12 db with respect to the typical gain -18 db with respect to the typical gain speaker receive off(sw21 off) speaker receive on (sw21 on) typical receive pad gain (0 db) -3 db with respect to the typical gain -6 db with respect to the typical gain -9 db with respect to the typical gain typical incoming tone gain (0 db) -10 db with respect to the typical gain -20 db with respect to the typical gain additional speaker gain = vol6 speaker amp. gain and additional speaker gain are set at a time. at the initial setting, sw21-off and the typical gain are set. receive pad = vol10 incoming tone gain = vol11, vol12 receive pad and incoming tone gain are set at a time. at the initial setting, the typical gain is set.
? semiconductor msm7502 30/35 key scanning signal output control write mode address data ad1 = 1, ad0 = 0 db7 the data set on db7 to db0 are output on po7 to po0 respectively. output data is held until next data is written. when the set data is set to "0", output data goes to "0", when set to "1", output pin becomes open. at the initial setting, po7 to po0 are in open state. db6 db5 db4 db3 db2 db1 db0 controlo data description for control output data key scanning data read out read mode address data ad1 = 1, ad0 = 0 db7 data input onto pi7 to pi0 are output onto db7 to db0. db6 db5 db4 db3 db2 db1 db0 contorol data description for control pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0 key scanning interrupt reset write mode address data ad1 = 1, ad0 = 1 db7 intt output is reset (output = 1) db6 db5 db4 db3 db2 db1 db0 control data description for control 01 000000 valid during write mode only remarks
? semiconductor msm7502 31/35 special functions write mode address data ad1 = 1, ad0 = 1 db7 vlcd pin output voltage : 0.0 v db6 db5 db4 db3 db2 db1 db0 contorol data description for control remarks lcd deflection angle control voltage output 000 001 010 011 100 101 110 111 01000 : 0.30 v : 0.55 v : 0.85 v : 1.1 v : 1.3 v : 1.5 v : 1.7 v at the initial setting stage, set to 0 v. power down mode control whole system power down mode 00 01 10 11 whole system power on mode codec power down mode codec power on mode 100000 at the initial setting stage, set to whole system power down mode. codec power on/off control is valid in the whole system power on mode. codec control codec operates in m -law 0 1 0 1 codec operates in a-law pcmin and pcmout are normally connected pcmout is connected to pcmin 110000 at the initial setting stage, set to m -law, and pcmin and pcmout are normally connected. the componding law and the connection control are set at a time. *2: even during the whole system power down mode, following functions are available, if xsync is input. : key scanning data i/o, sounder outputs (sa0, sa1), wdt, intt, and general latch output (la, lb)
? semiconductor msm7502 32/35 application circuit line line interface controller hold tone generator *1 *2 inserting a capacitor (1 m f to 22 m f) between sgt and ag will improve the transmit path noise characteristic. insert a resistor if necessary. *1 *2 100 k w speaker handset sgt tpai cao r1i rpo rmi rmo0 rmo1 spo spi sao 100 k w 0.1 m f 100 k w 0.1 m f +5 v +5 v 0 v 0.1 m f to 1 m f 0.1 m f 10 m f + +5 v lml pcmout pcmin bclock xsync wrn rdn cen resetn ad0 ad1 intt timen rsync db0 to db7 mpai tpao tpbi mpbi mpbo mpao to cai mldyi po0 po1 po2 po3 po4 po5 po6 po7 sw matrix pi0 pi1 pi2 pi3 pi4 pi5 pi6 pi7 sgc ag dg va vd 0-20 w
? semiconductor msm7502 33/35 msm7502 speech path level setting tpao mldyi to cai tpbi mpao mpai + C 20 db ain aout codec rmo0 r1i cao tpai spo rmo1 mpbi mpbo r2i 0 db spi sw5 sw5 sw1 sw2 sw7 sw16 5.7 db 0 db vol 3 vol 4 rpo rmi sw21 sw20 sw11 sw15 vol 5 vol 12 vol 11 C 22 db sw18 C 6.8 db sw10 vol 6 sw8 C 3 db sw6 0 db sw3 vol 1 sw4 vol 2 sw13 vol 7 sw17 C 8.7 db sw14 0 db sw9 0 db C 20 db to +25 db variable range step width typical level vol no. C14 db to 0 db C21 db to C3 db C11 db to C2 db C5 db to +4 db C28 db to 0 db C6 db C9 db C2 db +4 db 0 db 0 db 0 db +12 db +20 db 0 db 0 db 0 db vol 6 vol 7 vol 8 vol 9 vol 10 vol 11 vol 12 vol 1 vol 2 vol 3 vol 4 vol 5 C18 db to 0 db 90 mv to 180 mv +3 db to +12 db +11 db to +20 db C9 db to 0 db C20 db to 0 db C20 db to 0 db 2 db 3 db 3 db 3 db 4 db 6 db 30 mv 3 db 3,6 db 3 db 10 db 10 db vol 10 vol 9 vol 8 C + + C C C codec i/o level overload point: 1.2 v op 0 dbmo : 0.6007 vrms (C4.4 dbv) pb gen. per wave 0.24 v pp (C21.4 dbv equivalent) r-tone gen. 90 mv pp pulse (C27.8 dbv equivalent) f-tone gen. 0.16 v pp pulse (C22.8 dbv equivalent) s-tone gen. 0.22 v pp pulse (C20.0 dbv equivalent) C C C
? semiconductor msm7502 34/35 recommendations for actual design ? to assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the va and ag pins. ? connect the ag pin and the dg pin each other as close as possible. connect to the system ground with low impedance. ? connect the va pin and the vd pin as close together as possible and route them to the analog 5 v power supply. ? mount the device directly on the board when mounted on pcbs. do not use ic sockets. if an ic socket is unavoidable, use the short lead type socket. ? when mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. ? keep the voltage on the v dd pin not lower than C0.3 v even instantaneously to avoid latch-up phenomenon when turning the power on. ? use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. ? connect analog input pins and digital input pins that are not used to the sg pin and to gnd, respectively. ? when the data is written differently from the data defined in the section, control data description in functional description, normal device operation is not guaranteed.
? semiconductor msm7502 35/35 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp80-p-1420-0.80-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.27 typ. mirror finish

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